This course, which is the third one of a “series”, is for anyone passionate about learning the theory on how to develop FPGA-accelerated applications with SDAccel. We are entering an era in which technological progress induces paradigm shifts in computing.
As a tradeoff between the two extreme characteristics of GPP and ASIC, we can find a new concept, a new idea of computing... the reconfigurable computing, which has combined the advantages of both the previous worlds. Within this context, we can say that reconfigurable computing will widely, pervasively, and gradually impact human lives. Hence, it is time that we focus on how reconfigurable computing and reconfigurable system design techniques are to be utilised for building applications.
On one hand reconfigurable computing can have better performance with respect to a software implementation but paying this in terms of time to implement. On the other hand a reconfigurable device can be used to design a system without requiring the same design time and complexity compared to a full custom solution but being beaten in terms of performance.
Within this context, the Xilinx SDx tools, including the SDAccel environment, the SDSoC environment, and Vivado HLS, provide an out-of-the-box experience for system programmers looking to partition elements of a software application to run in an FPGA-based hardware element, and having that hardware work seamlessly with the rest of the application running in a processor or embedded processor.
The out-of-the-box experience will provide interesting and, let us say, “good enough” results for many applications.
However, this may not be true for you, you may be looking for better performance, data throughput, reduced latency, or to reduce the resources usage...
This course is focusing on this. After introducing you to the FPGAs we are going to dig more into the details on how to use Xilinx SDAccel providing you also with working examples on how to optimize the hardware logic to obtain the best of of your hardware implementations. In this case, certain attributes, directives, or pragmas, can be used to direct the compilation and synthesis of the hardware kernel, or to optimise the function of the data mover operating between the processor and the hardware logic.
Furthermore, in this course we are going to focus on distributed, heterogeneous infrastructures, presenting how to bring your solutions to life by using the Amazon EC2 F1 instances.
Prerequisites
This course follows the previous ones “FPGA computing systems: A Bird’s Eye View on Reconfigurable Computing” and “FPGA computing systems: Partial Dynamic Reconfiguration”. Within this context no specific background knowledge is requested. Anyone with moderate computer experience should be able to master the materials in this course.
