The course begins with a lesson on performance measurement, which leads to a discussion on the necessity of performance improvement. Pipelining, the first level of performance refinement, is reviewed. The weaknesses of pipelining will be exposed and explored, and various solutions to these issues will be studied. The student will learn hardware, software, and compiler based solutions to these issues.
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You will explore the fascinating field of computer architecture, studying the many methods developed to enhance computer performance. The trade-offs and compromises associated with each design and their effects on processor development is a captivating story that will make you a better computer scientist, regardless of your field of study.
What you will learn
- Introduction and Trends
- Computer Architecture & Tech Trends
- Moore's Law
- Processor Speed, Cost, Power
- Power Consumption
- Fabrication Yield
- Performance Metrics and Evaluation
- Measuring Performance
- Benchmarks Standards
- Iron Law of Performance
- Amdahl's Law
- Lhadma's Law
- Pipelining Review
- Pipeline CPI
- Processor Pipeline Stalls
- Data Dependencies
- Pipelining Outro
- Branches
- Branch Prediction
- Direction Predictor
- Hierarchical Predictors
- PShare
- Predication
- If Conversion
- Conditional Move
- MOVc Summary
- Instruction Level Parallelism (ILP)
- ILP Intro
- RAW Dependencies
- WAW Dependencies
- Duplicating Register Values
- Instruction Level Parallelism (ILP)
- Instruction Scheduling
- Improving IPC
- Tomasulo's Algorithm
- Load and Store Instructions
- ReOrder Buffer
- Exceptions in Out Of Order Execution
- Branch Misprediction
- Hardware Organization with ROB
- Memory Ordering
- Memory Access Ordering
- When Does Memory Write Happen
- Out of Order Load Store Execution
- Store to Load Forwarding
- LSQ, ROB, and RS
- Memory
- How Memory Works
- One Memory Bit SRAM
- One Memory Bit DRAM
- Fast Page Mode
- Connecting DRAM To The Processor
- Multi-Processing
- Flynn's Taxonomy of Parallel Machines
- Multiprocessor Needs Parallel Programs!
- Centralized Shared Memory
- Distributed Shared Memory
- Message Passing Vs Shared Memory
- Shared Memory Hardware
- SMT Hardware Changes
- SMT and Cache Performance
Prerequisites and requirements
You must be familiar with Assembly code, the C or C++ programming language, Unix or Linux, and the basics of pipelining.
